System on an FPGA in a Unified Design Environment

Volker Brandstetter, Joerg Kaleita
Altium Europe GmbH

Todays engineers have to handle different design approaches like generating PCBs, develop complete systems on FPGA and writing embedded software arround this system. All of this is seperated into different domains and handled with a point-tool-approach. Altium Designer is breaking the chains of this traditional approach. In a Unified Design Environment, all domains will work on the same database. This approach enables engineers to optimize a pinning on PCB automatically. Synchronize the new pinning with schematic and constraints for the FPGA is only a few mouse clicks away. Additionaly, with a direct 'Live Design' link to the inside of an FPGA, values can be read and set for a new way of debugging and interfacing to a design. Even complex systems can be designed in hours enabled by concepts like OpenBus and the Software Platform Builder. Included are free IPs, drivers, services and embedded software up to the application layer (e.g. TCP/IP stack). This can be tested and executed in a perfectly integrated prototyping platform called Nanoboard.

The implementation of the generated design is vendor independent and has the same flow for e.g. Xilinx, Altera, Lattice and Actel. Therefore engineers do not need to learn the handling of this tools necessarily. The vendor tools will nevertheless be used in batch mode for being able to do so.

Altium Designer has a very abstract and transparent graphical way of design entry. In times of highly complex systems on FPGA, this is a clear advantage of using plain HDL. Still, the engineer can use his existing HDL code (VERILOG and VHDL). Additionaly, engineers can use a powerfull integrated C-to-Hardware engine allowing design entry in C. Therefore e.g. available code and libraries for filter algorithms etc. can be used without the need to translate them into HDL.

With this engine, the user can decide for each function written to let it run on the sequential Soft CPU or in a concurrent FPGA implementation. Just imagine a simple for-loop with 100 cycles implemented sequential or parallel show the optimization capabilities for speed requirements. The limit of this approach is only the amount of memory delivered with the FPGA used.

In this presentation, you will get 5 reasons, why you should develop your next System on FPGA with Altium Designers

This talk will be presented on Tuesday in slot T1B3.