Workshops

Xilinx Professor Workshop on embedded Linux on Xilinx MicroBlaze

Date: September 3-4, 2009
Time: 9:00-17:00 both days
Location: Brno University of Technology, Laboratory Room L306
Instructor: Parimal Patel

Online Registration (max. 40 participants)

Xilinx University Program (XUP) is pleased to announce Professor Workshop on Embedded Linux using Xilinx MicroBlaze at Brno University of Technology, Brno, Czech Republic, to be held on September 3-4, 2009. This workshop will provide university academics with the resources, high level skills and confidence to introduce embedded Linux on Xilinx MicroBlaze to their teaching and research programs. The workshop uses Xilinx EDK 10.1.03, ISE 10.1.03, and PetaLinux Linux distribution tree software tools. The workshop includes lecture and hands-on laboratory experience using Spartan3E1600 board.

The workshop is open to academics and is free to attend but requires registration. To register, visit http://www.xilinx.com/univ/uwkshp.htm and click on Workshop Schedule from the right-side navigation column. You can become a XUP member when asked for login name if you are not already a member. Once registered, you will be sent a confirmation e-mail confirming your registration.

Thank you for being XUP member.
Regards,
XUP Team

NetFPGA Workshop

Date: September 3-4, 2009
Time: 9:00-17:00 both days
Location: Brno University of Technology, Laboratory Room L314
Instructor: John Lockwood, Martin Zadnik, Jan Korenek, Jiri Novotny

Online Registration (max. 20 participants)

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware- accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Protocol (IP) routers using hardware rather than software and can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

The NetFPGA enables to implement highly accurate network monitoring devices. During the tutorial, we will demonstrate how to use NetFPGA for wire-speed monitoring based on CISCO NetFlow technology, which is widely used for accounting, billing, network capacity planning or intrusion detections. An example of FPGA based industrial solution for NetFlow monitoring will be shown on family of COMBO cards.

This two-days hands-on tutorial will be held in a laboratory equipped with ten PCs with NetFPGA hardware. More information together with a detailed schedule can be found at http://www.liberouter.org/netfpga/2009/.

Enhancing Education with Altera's Technology and Teaching Materials

Date: August 30, 2009
Time: 9:00-12:00, 13:00-16:00
Location: UTIA, Czech Academy of Sciences, Room 025
Instructor: Tom Czajkowski

Registration (max. 20 participants) - contact Tom Czajkowski

This workshop introduces Altera's technology and teaching materials developed specifically for use in Digital Logic and Computer Organization courses. We will give an overview of Altera's FPGA technology, and its application in an educational setting. We will concentrate on the use of Quartus II software and a hardware platform based on Altera's DE1/DE2 boards. Participants will have an opportunity to implement logic circuits on these boards, which were designed for use in educational environments.

We will demonstrate how Quartus II CAD software can be used to design and implement logic circuits that can be downloaded onto a DE1/DE2 board. The discussion will include the use of debugging facilities included in Quartus II software, such as the RTL (Register Transfer Level) Viewer and the SignalTap II Embedded Logic Analyzer.

Next, we will discuss how a computer system can be implemented on the DE1/DE2 board. This involves using the System-on-Programmable-Chip (SOPC) Builder tool and the Nios II soft-core processor. We will show how application programs written in either the Nios II assembly language or the C programming language can be compiled, downloaded and run. This will be done with the Altera Monitor Program, which provides the facilities for implementation and debugging of application programs.

If attendees wish to use their own laptops during the workshop, then they should download and install software found at www.altera.com prior to the tutorial. In particular, attendees should download and install:

Quartus II 9.0 web edition
Nios II Embedded Design Suite 9.0
Altera Monitor Program

The first two packages are available in the Download Center, which has a link at the top right corner of www.altera.com. The Altera Monitor Program is available on the University Program section of Altera's website. It can be found by opening the web page university.altera.com and clicking on the link called Design Software in the Educational Materials area of the web page.

We will provide Altera DE1 boards for use in the hands-on part of the tutorial.

At the end of the tutorial we will give away Altera DE1 boards to professors and instructors who attend the session.

Tutorial on Partial Runtime Reconfiguration using the ReCoBus-Builder

Date: August 30, 2009
Time: 16:15-19:00
Location: UTIA, Czech Academy of Sciences, Room 3
Instructor: Dirk Koch, Christian Beckhoff

Online registration (max. 20 participants) (see the bottom of the page)

In this tutorial, attendees will learn step by step how to implement a complex runtime reconfigurable system on the Xilinx XUPV2P board using the novel tool ReCoBus-Builder. This tool was developed at the University of Erlangen-Nuremberg and was released at the last FPL. It opens a new dimension in usability, flexibility, performance, and efficiency in building partial reconfigurable systems on Xilinx FPGAs.

The tutorial will show that less than three hours are sufficient to smoothly build a system providing an embedded PPC, external SDRAM memory, a bench of peripherals, and a ReCoBus-subsystem. The ReCoBus will directly connect reconfigurable slave and master modules (with DMA capability) with the rest of the system. Different groups will implement partial modules that will then be integrated to one final system. This system may contain more than 40 individually addressable modules that may all manipulate a video stream. Attendees will learn how easy self-reconfiguration and component-based system design can be implemented using the Xilinx design tools together with the ReCoBus-Builder.

Please visit the project website http://www.recobus.de for evaluating the tool and for lots of further information.

Travel Arrangements

How to get to the workshops at UTIA

The Prague public transport is very comfortable. The best way to get to UTIA is to take Metro "C" (the red line) to Ladvi. UTIA is a 5 minutes walk from there. The way is marked by a red line on the map here.

How to get to the workshops in Brno

A special coach will take people on Wednesday afternoon and bring them back on Friday (expected departure from Brno after 5:00 PM) to Prague.
The coach will depart on Wednesday afternoon from the conference venue in Prague and arrive at Hotel Slovan in Brno. On the way back, the coach will make two stops - one at the Prague main railway station with a direct bus connection to the Prague Airport (public transport bus "AE"), and another at Hotel Don Giovanni.
Workshop participants are required to make room reservations in Hotel Slovan on their own (2 nights), a special rate has been negotiated for reservations made before July 21 (reservation code FPL2009).