Customizable Domain-Specific Computing

Jason Cong
UCLA Computer Science Department

In order to meet ever-increasing computing needs and overcome power density limitations, the computing industry has halted simple processor frequency scaling and entered the era of parallelization, with tens to hundreds of computing cores integrated in a single processor, and hundreds to thousands of computing servers connected in a warehouse-scale data center. However, such highly parallel, general-purpose computing systems still face serious challenges in terms of performance, power, heat dissipation, space, and cost. In this talk, I suggest that we look beyond parallelization and focus on domain-specific customization as the next opportunity to bring orders-of-magnitude power-performance efficiency improvement to important classes of applications. This challenge requires a great deal of innovation in architecture, compilation, and runtime system design, and offers many exciting and challenging research opportunities. I shall highlight some promising developments in direction so far and discuss various opportunities for the FPL research community.

In Search of Agile Hardware

Peter Athanas
Configurable Computing Lab
Virginia Tech

In an engineering perspective, agility is one property that a designer must consider when creating a product that is expected to undergo change throughout its lifetime. For embedded computing systems, traditionally the system hardware is fixed, and the system software provides the means of achieving agility. Altering software functionality is relatively easy to do, and software compile times are fast. There are situations, however, where for performance reasons, agility beyond software is needed. In theory, FPGAs offer a degree of agility to system hardware through the mechanism of altering functionality under software control. In practice, however, FPGAs are not very agile at all, requiring long design times and complicated compilation processes. In this talk, the use-model of contemporary FPGAs is reexamined, and alternative ways of hardware/software interaction are presented with the objective of achieving a higher degree of hardware agility.

The Evolution of Architecture Exploration of Programmable Devices

Jonathan Rose
The Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto

As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that question is the global organization of the structures created from the transistors, most commonly referred to as the *architecture* of the device.

Most IC architecture exploration that is done is quite empirical, with example uses driving through tools to experimentally test new ideas for structures and organizations. This method is used in both programmable logic hardware such as FPGAs, and in programmable instruction set processors. As the processor world now seeks to gain performance through parallelism, its architecture questions have begun to look more similar to those in the FPGA domain.

In this talk I discuss the evolution of the architecture exploration processes that we have worked on at the University of Toronto, and of the new levels that we are currently trying to build. The current effort focusses on HDL-level circuits as "example uses" and this turns out to be rather intricate in the face of the kinds of architecture questions that could be posed. In the future, it may well be that some form of software is the input "example use," thus bringing the processor and FPGA world closer together. For this to work, there needs to be an effective CAD/compiler flow from software to the HDL level. I will give perspective on the state of this art, and discuss what kind of commonality might evolve in architecture exploration tools for FPGAs and processors.

FPGA Challenges and Opportunities at 40nm and Beyond

Vaughn Betz
Altera

FPGA companies are amongst the earliest adopters of next-generation process technology. This involves many challenges, including power management, device modeling, increasing I/O performance to match the computational capacity, and enabling very large designs to be completed quickly.

Process scaling increases FPGA capacity and allows new features, such as high-performance I/O protocols (e.g. PCI Express). Scaling favours FPGAs over competing technologies, as fewer and fewer ASICs have the volumes to justify the cost of a design in cutting-edge technology.

I will give an overview of the challenges in designing a cutting-edge FPGA, and describe the solutions Altera has adopted in its 40nm Stratix IV FPGAs. I/O bandwidth is crucial. While the density of FPGAs is increasing rapidly, the number of I/O pins is not -- we need to move more bits through the same number of pins. Another challenge is to model the timing, power and signal integrity of increasingly complex FPGAs in increasingly variable processes, while still keeping the tools easy to use. Managing power is a third challenge. Each process generation roughly doubles the number of transistors per die and tends to increase leakage power. The power budget per FPGA is roughly constant, so we need to innovate to control power.

Ever larger FPGAs also necessitate innovation to keep designers productive. We must both keep the compile time of traditional FPGA CAD tools reasonable, and develop new tools that allow designers to create and verify more complex systems in the same time.

Virtex-6 and Spartan-6, Plus a Look into the Future.

Peter Alfke
Xilinx

Recently, Xilinx introduced two new FPGA families, Virtex-6 and Spartan-6, closely related in architecture, but each optimized for different markets and applications: Virtex-6 for high performance, features and capacity; Spartan-6 for low cost and low power consumption. Both families take advantage of 40/45 nm technology, and both are derived from the successful Virtex-5 architecture.

I will give an overview of the salient features and capabilities of both families. Then I will give a peek into the future, explaining the impact of rapidly rising development costs for all future technology nodes. That limits ASICs and ASSPs to serve only high-volume opportunities, and offers unique advantages for FPGAs. But we must overcome certain technical difficulties, and streamline the user's design process.