Download a PDF version of the program here.
| Monday, August 31 | |||
| 8:30-8:45 | Opening | ||
| 8:45-9:40 | Keynote 1 - Jason Cong: Customizable Domain-Specific Computing | ||
| 9:45-11:15 | Threads, MPI, Multi-CPU Systems | Practical Applications | Acceleration |
| Session chair: Dionisios Pnevmatikatos | Session chair: Stephan Stilkerich | Session chair: Alastair Smith | |
| 9:45 | M1A1 | M1B1 | M1C1 |
| MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda and Hideharu Amano |
A Biophysically Accurate Floating Point Somatic Neuroprocessor Yiwei Zhang, José Nuñez-Yañez, Joe McGeehan, Edward Regan and Stephen Kelly |
Compiler Assisted Runtime Task Scheduling on a Reconfigurable Computer Mojtaba Sabeghi, Vlad-Mihai Sima and Koen Bertels |
|
| 10:15 | M1A2 | M1B2 | M1C2 |
| Hardware Implementation of MPI Barrier on an FPGA Cluster Shanyuan Gao, Andrew G. Schmidt and Ron Sass |
CNP: An FPGA-based Processor for Convolutional Networks Clément Farabet, Cyril Poulet, Yann LeCun and Jefferson Y. Han |
Data Parallel FPGA Workloads: Software Versus Hardware Peter Yiannacouras, J. Gregory Steffan and Jonathan Rose |
|
| 10:45 | M1A3 | M1B3 | M1C3 |
| Fast Critical Sections via Thread Scheduling for FPGA-based Multithreaded Processors Martin Labrecque and J. Gregory Steffan |
Noise Impact of Single-Event Upsets on an FPGA-based Digital Filter Brian H. Pratt, Michael J. Wirthlin, Michael Caffrey, Paul Graham and Keith Morgan |
Generating High-Performance Custom Floating-Point Pipelines Florent de Dinechin, Cristian Klein and Bogdan Pasca |
|
| 11:15-11:45 | Break & Poster Session 1 | ||
|
P1.1
Building Heterogeneous Reconfigurable Systems Using Threads
Jason Agron and David Andrews
P1.2
Reconfiguration-based Time-to-Digital Converter for Virtex FPGAs.
Ángel Quirós-Olozábal, Juan Manuel Barrientos-Villar and Mª de los Ángeles Cifredo-Chacón
P1.3
An Efficient Reconfigurable Architecture to Implement Dense Stereo Vision Algorithm Using High-Level Synthesis.
Mario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard, Pierre Lacroix and Jean-Yves Fourniols
P1.4
High Speed Fixed Point Dividers for FPGAs
Gustavo Sutter and Jean-Pierre Deschamps
P1.5
A Self Reconfiguring Architecture Supporting Multiple Objective Functions in Genetic Algorithms
Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas and Ioannis Papaefstathiou
P1.6
Automatic Generation of FPGA Hardware Accelerators Using a Domain Specific Language
Ricardo Menotti, João M. P. Cardoso, Marcio Fernandes and Eduardo Marques
P1.7
A Dynamically Reconfigurable Parallel Pixel Processsing System
Daniel Llamocca, Marios Pattichis and Alonzo Vera
P1.8
An Approach to System-Wide Fault Tolerance for FPGAs
Jano Gebelein, Heiko Engel and Udo Kebschull
P1.9
A Multi-Layered XML Schema and Design Tool for Reusing and Integrating FPGA IP
Adam Arnesen, Nathaniel Rollins and Michael Wirthlin
P1.10
Bitstream Compression Through Frame Removal and Partial Reconfiguration
Benjamin Sellers, Jonathan Heiner, Michael Wirthlin and Jeff Kalb
P1.11
Operation Scheduling for FPGA-based Reconfigurable Computers
Colin Yu Lin, Ngai Wong and Hayden Kwok-Hay So
P1.12
FPGA-Accelerated Retinal Vessel-Tree Extraction
Alejandro Nieto, Victor Brea and David López Vilariño
P1.13
Novel Strategies for Hardware Acceleration of Frequent Itemset Mining with the Apriori Algorithm
David W. Thöni and Alfred Strey
| |||
| 11:50-12:50 | Keynote 2 - Peter Athanas: In Search of Agile Hardware | ||
| 12:55-13:55 | LUNCH | ||
| 14:00-15:30 | GPU, CPU, FPGA Register Allocation | Partial Runtime Reconfiguration | Synthesis, Low Power |
| Session chair: Fabrizio Ferrandi | Session chair: Michael Hübner | Session chair: José Nuñez-Yañez | |
| 14:00 | M2A1 | M2B1 | M2C1 |
| Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors Nachiket Kapre and Andre DeHon |
A Runtime Relocation Based Workflow for Self Dynamic Reconfigurable Systems Design Marco Domenico Santambrogio, Massimo Morandi, Marco Novati and Donatella Sciuto |
Improving Logic Density Through Synthesis-Inspired Architecture Jason H. Anderson and Qiang Wang |
|
| 14:30 | M2A2 | M2B2 | M2C2 |
| Exploring Reconfigurable Architectures for Explicit Finite Difference Option Pricing Models Qiwei Jin, David Thomas and Wayne Luk |
An Integrated Tool Flow to Realize Runtime-Reconfigurable Applications on a New Class of Partial Multi-Context FPGAs Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf and Manfred Glesner |
Clock Gating Architectures for FPGA Power Reduction Safeen Huda, Muntasir Mallick and Jason Anderson |
|
| 15:00 | M2A3 | M2B3 | M2C3 |
| Towards a Viable Out-of-order Soft Core: Copy-Free, Checkpointed Register Renaming Kaveh Aasaraai and Andreas Moshovos |
FPGA Partial Reconfiguration via Configuration Scrubbing Jonathan Heiner, Benjamin Sellers, Michael Wirthlin and Jeff Kalb |
Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh Heiner Giefers and Marco Platzner |
|
| 15:30-16:00 | Break & Poster Session 2 | ||
|
P2.1
Dynamic Polymorphic Reconfiguration for Anti-Tamper Circuits
Roy Porter, Samuel J. Stone, Yong C. Kim, J. Todd McDonald and LaVern Starman
P2.2
Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
Ming Liu, Wolfgang Kuehn, Zhonghai Lu and Axel Jantsch
P2.3
Dynamic Reconfigurable Mixed-Signal Architecture for Safety Critical Applications
Romuald Girardey, Michael Hübner and Jürgen Becker
P2.4
Using 3D Integration Technology to Realize Multi-Context FPGAs
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici and Paolo Ienne
P2.5
MEMS Optically Reconfigurable Gate Array
Hironobu Morita and Minoru Watanabe
P2.6
SHARF: An FPGA-based Customizable Processor Architecture
Cem Savas Bassoy, Henning Manteuffel and Friedrich Mayer-Lindenberg
P2.7
Multigigabit Network Traffic Processing
Jiří Halák
P2.8
MACS: A Minimal Adaptive Routing Circuit-Switched Architecture for Scalable and Parametric NoCs
Rohit Kumar and Ann Gordon-Ross
P2.9
Fine Grain Partial Reconfiguration for Energy Saving in Dynamically Reconfigurable Processors
Toru Sano, Yoshiki Saito, Masaru Kato and Hideharu Amano
P2.10
A Low Cost Reconfigurable Soft Processor for Multimedia Applications: Design Synthesis and Programming Model
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit and Martin Margala
| |||
| 16:00-17:30 | GPU, CPU, FPGA and Image Processing | Placement and Routing | Applications #1 |
| Session chair: David Thomas | Session chair: Katherine Compton | Session chair: Ron Sass | |
| 16:00 | M3A1 | M3B1 | M3C1 |
| Performance Comparison of FPGA, GPU and CPU in Image Processing Shuichi Asano, Tsutomu Maruyama and Yoshiki Yamaguchi |
An Analytical Model Relating FPGA Architecture and Place and Route Runtime Scott Y. L. Chin and Steve J. E. Wilton |
A Multi-FPGA Architecture for Stochastic Restricted Boltzmann Machines Daniel L. Ly and Paul Chow |
|
| 16:30 | M3A2 | M3B2 | M3C2 |
| Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging Stefan Wildermann, Gregor Walla, Tobias Ziermann and Jürgen Teich |
RePlace: An Incremental Placement Algorithm for Field-Programmable Gate Arrays David Leong and Guy G. F. Lemieux |
Comparing Fine-Grained Performance on the Ambric MPPA Against an FPGA Brad Hutchings, Brent Nelson, Stephen West and Reed Curtis |
|
| 17:00 | M3A3 | M3B3 | M3C3 |
| Optimizing the SUSAN Corner Detection Algorithm for a High Speed FPGA Implementation Christopher Claus, Robert Huitl, Joachim Rausch and Walter Stechele |
Optimal Runtime Reconfiguration Strategies for Systolic Arrays Arpith C. Jacob, Jeremy D. Buhler and Roger D. Chamberlain |
Low Power Techniques for Motion Estimation Hardware Caglar Kalaycioglu, Onur Ulusel and Ilker Hamzaoglu |
|
| 17:30-18:00 | PhD Forum | ||
|
PF1.1
High-level Programming of Coarse-grained Reconfigurable Architectures
Zain Ul-Abdin
PF1.2
FPGA Support for Satellite Computations of Hyper Spectral Images
Carlos González, Javier Resano and Daniel Mozos
PF1.3
Improving the Memory Footprint and Runtime Scalability of FPGA CAD Algorithms
Scott Chin and Steve Wilton
PF1.4
Efficient Techniques and Methodologies for Embedded System Design usign Free Hardware and Open Standards
Jose I. Villar de Ossorno, Jorge Juan Chico and Manuel Jesus Bellido Diaz
PF1.5
Multi-Terminal BDD Synthesis and Applications
Petr Mikušek
PF1.6
Soft Errors in Flash-Based FPGAs: Analysis, Methodologies and First Results
Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone and Massimo Violante
PF1.7
RISPP: A Run-Time Adaptive Reconfigurable Embedded Processor
Lars Bauer, Muhammad Shafique and Jörg Henkel
| |||
| 20:00 | WELCOME DRINK | ||
| Tuesday, September 1 | |||
| 8:45-9:40 | Keynote 3 - Jonathan Rose: The Evolution of Architecture Exploration of Programmable Devices | ||
| 9:45-11:15 | Fault Toleance and Reliability | FPGA Architectures | Surveys, Trends |
| Session chair: Udo Kebschull | Session chair: Jason Andersen | Session chair: Carlos Valderrama | |
| 9:45 | T1A1 | T1B1 | T1C1 |
| Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability Dawood Alnajjar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi and Takao Onoye |
Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth Joydip Das, Steven J. E. Wilton, Philip Leong and Wayne Luk |
An ASIC Perspective on FPGA Optimizations Andreas Ehliar and Dake Liu |
|
| 10:15 | T1A2 | T1B2 | T1C2 |
| A Novel SRAM-Based FPGA Architecture for Efficient TMR Fault Tolerance Support Konstantinos Kyriakoulakos and Dionisios Pnevmatikatos |
Globally Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Systems Masato Inagi, Yasuhiro Takashima and Yuichi Nakamura |
Recursion in Reconfigurable Computing: A Survey of Implementation Approaches Iouliia Skliarova and Valery Sklyarov |
|
| 10:45 | T1A3 | T1B3 | T1C3 |
| Reconfigurable Fault Tolerance: A Framework for Environmentally Adaptive Fault Mitigation in Space Adam Jacobs, Alan D. George and Grzegorz Cieslewski |
INDUSTRIAL TALK - System on an FPGA in a Unified Design Environment V. Brandstetter and J. Kaleita |
A Comparison of FPGA and FPAA Technologies for a Signal Processing Application Roberto Selow, Heitor S. Lopez and Carlos R. Erig Lima |
|
| 11:15-11:45 | Break & Poster Session 3 | ||
|
P3.1
Rapid Design Exploration Framework for Applciation-Aware Customization of Soft Core Processors Alok Prakash, Siew Kei Lam, Amit Singh and Thambipillai Srikanthan
P3.2
A Novel States Recovery Technique for the TMR Softcore Processor Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga and Toshinori Sueyoshi
P3.3
Performance Metrics for Hybrid Multi-Tasking Systems Kyle Rupnow, Jacob Adriaens, Wenyin Fu and Katherine Compton
P3.4
Cooperative Multithreading in Dynamically Reconfigurable Systems Enno Lübbers and Marco Platzner
P3.5
The Educational Processor SWEET-16 Venelin Angelov and Volker Lindenstruth
P3.6
Secure FPGA Technologies and Techniques An Braeken, Serge Kubera, Frederik Trouillez, Abdellah Touhafi, Jo Vliegen and Nele Mentens
P3.7
FPGA Supercomputer Platforms: A Survey Mariette Awad
P3.8
A Novel SEU, MBU and SHE Handling Strategy for Xilinx Virtex-4 FPGAs Xabier Iturbe, Mikel Azkarate, Imanol Martínez, Jon Perez and Armando Astarloa
P3.9
Run-Time Resource Management in Fault-Tolerant Network on Reconfigurable Chip Mohammad Hosseinabady and Jose Nunez-Yanez
P3.10
Hot-Swapping Architecture Extension for Mitigation of Permanent Functional Unit Faults Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi and Yukihiro Nakamura
P3.11
SVM Speaker Verification System Based on a Low-Cost FPGA Rafael Ramos-Lara, Mariano López-García, Enrique Cantó-Navarro and Luis Puente-Rodriguez
P3.12
An FPGA-Based Embedded Wideband Audio CODEC System Chang Choo, Bhavya Bambhania, Woon-Seob So, In-Ki Hwang and Do-Young Kim
| |||
| 11:50-12:50 | Keynote 4 - Vaughn Betz: FPGA Challenges and Opportunities at 40nm and Beyond | ||
| 12:55-13:55 | LUNCH | ||
| 14:00-15:30 | Arithmetic | Interconnect (classical) | Image Processing Applications |
| Session chair: Pavel Zemčík | Session chair: Andreas Koch | Session chair: Tom VanCourt | |
| 14:00 | T2A1 | T2B1 | T2C1 |
| A Radix-8 Complex Divider for FPGA Implementations Dong Wang, Miloš D. Ercegovac and Nanning Zheng |
Area Estimation and Optimization of FPGA Routing Fabrics Alastair M. Smith, George A. Constantinides and Peter Y. K. Cheung |
A Fast Parallel Matrix Multiplication Reconfigurable Unit Utilized in Face Recognition Systems Ioannis Sotiropoulos and Ioannis Papaefstathiou |
|
| 14:30 | T2A2 | T2B2 | T2C2 |
| Exploiting Fast Carry-Chains of FPGAs for Designing Compressor Trees Hadi Parandeh-Afshar, Philip Brisk and Paolo Ienne |
In Field Energy-Performance Tunable FPGA Architectures Bita Nezamfar and Mark Horowitz |
Design Space exploration of Reconfigurable Systems for calculating Flying Object's Optimal Noise Reduction Paths Dimitrios Kontos, Ioannis Papaefstathiou and Dionisios Pnevmatikatos |
|
| 15:00 | T2A3 | T2B3 | T2C3 |
| Large Multipliers with Fewer DSP Blocks Florent de Dinechin and Bogdan Pasca |
Static versus Scheduled Interconnect in Coarse-Grained Reconfigurable Arrays Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling and Scott Hauck |
Real-Time Processing of Local Contrast Enhancement on FPGA Kentaro Kokufuta and Tsutomu Maruyama |
|
| 15:30-16:00 | Break & Poster Session 4 | ||
|
P4.1
Off-Line Placement of Hardware Tasks on FPGA Ikbel Belaid, Fabrice Muller and Maher Benjemaa
P4.2
PROTEUS: An Architectural Synthesis Tool Based on the Stream Programming Paradigm Nikolaos Bellas, Sek Chai, Malcolm Dwyer, Dan Linzmeier and Abelardo Lopez-Lagunas
P4.3
Binary Synthesis with Multiple Memory Banks Targeting Array References Yosi Ben Asher and Nadav Rotem
P4.4
Mapping Basic Prefix Computations to Fast Carry-Chain Structures Thomas B. Preußer and Rainer G. Spallek
P4.5
FPGA Implementation of Time-Multiplexed Multiple Constant Multiplication Based on Carry-Save Arithmetic Roberto Gutierrez, Javier Valls and Asuncion Perez-Pascual
P4.6
Compensating for Variability in FPGAs by Re-Mapping and Re-Placement Pete Sedcole, Edward Stott and Peter Cheung
P4.7
Synthesis of the SR Programming Language for Complex FPGAs Nick Gasson and Neil Audsley
P4.8
Exploiting Synchronous Placement for Asynchronous Circuits onto Commercial FPGAs Maurizio Tranchero and Leonardo M. Reyneri
P4.9
Using C-to-Gates to Program Streaming Image Processing Kernels Efficiently on FPGAs. Kristof Denolf, Stephen Neuendorffer and Kees Vissers
P4.10
An FPGA based Verification Platform for HyperTransport 3.x Heiner Litz, Holger Fröning, Maximilian Thürmer and Ulrich Brüning
P4.11
A Virus Scanning Engine Using a Parallel Finite-Input Memory Machine and MPUs Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura and Yoshifumi Kawamura
P4.12
Tracking Elephant Flows in Internet Backbone Traffic with an FPGA-based Cache Martin Zadnik, Marco Canini, Andrew W. Moore, David Miller and Wei Li
| |||
| 16:00-17:30 | Methodologies | Interconnect (NoC) | Application Acceleration #1 |
| Session chair: João M. P. Cardoso | Session chair: Gerald Sobelman | Session chair: Yannis Papaefstathiou | |
| 16:00 | T3A1 | T3B1 | T3C1 |
| Enhancements to FPGA Design Methodology Using Streaming Franjo Plavec, Zvonko Vranesic and Stephen Brown |
sFPGA2 - A Scalable GALS FPGA Architecture and Design Methodology Rizwan Syed, Xiaolei Chen, Yajun Ha and Bharadwaj Veeravalli |
Accelerating HMMER Search Using FPGA Toyokazu Takagi and Tsutomu Maruyama |
|
| 16:30 | T3A2 | T3B2 | T3C2 |
| General Methodology for Mapping Iterarive Approximation Algorithms to Adaptive Dynamically Partially Reconfigurable Systems Josef Angermeier, Abdulazim Amouri and Jürgen Teich |
STAR-WHEELS Network-on-Chip Featuring a Self-Adaptive Mixed Topology and a Synergy of a Circuit- and a Packet-Switching Communication Protocol Diana Göhringer, Bin Liu, Michael Hübner and Jürgen Becker |
An Accelerator for K-th Nearest Neighbor Thinning Based on the IMORC Infrastructure Tobias Schumacher, Christian Plessl and Marco Platzner |
|
| 17:00 | T3A3 | T3B3 | T3C3 |
| Optimising Designs by Combining Model-based and Pattern-based Transformations Qiang Liu, Tim Todman, José Gabriel de F. Coutinho, Wayne Luk and George A. Constantinides |
A New Deadlock-free Fault-tolerant Routing Algorithm for NoC Interconnections Slavisa Jovanović, Camel Tanougast, Serge Weber and Christophe Bobda |
Efficient Particle-Pair Filtering for Acceleration of Molecular Dynamics Simulation Matt Chiu and Martin C. Herbordt |
|
| 19:30 | SOCIAL EVENT | ||
| Wednesday, September 2 | |||
| 9:00-9:55 | Keynote 5 - Peter Alfke: Virtex-6 and Spartan-6, plus a look into the future. | ||
| 10:00-11:30 | Applications #2 | Cryptography, Networking | Watermarking, Chip ID, IP Protection |
| Session chair: Mladen Berekovic | Session chair: Miloš Drutarovský | Session chair: Hana Kubátová | |
| 10:00 | W1A1 | W1B1 | W1C1 |
| Implementation of a Reconfigurable Fast Fourier Transform Application to Digital Terrestrial Television Broadcasting Florent Camarda, Jean-Christophe Prévotet and Fabienne Nouvel |
Pipeline Implementation of the 128-Bit Block Cipher CLEFIA in FPGA Tomasz Kryjak and Marek Gorgoń |
Increasing Stability and Distinguishability of the Digital Fingerprint in FPGAs through Input Word Analysis Hiren Patel, Yong Kim, Jeffrey McDonald and LaVern Starman |
|
| 10:30 | W1A2 | W1B2 | W1C2 |
| Design and Evaluation of an Energy-Efficient Dynamically Reconfigurable Architecture for Wireless Sensor Nodes Heiko Hinkelmann, Peter Zipf and Manfred Glesner |
Clock Duplicity for High-Precision Timestamping in Gigabit Ethernet Carles Nicolau, Dolors Sala and Enrique Cantó |
Towards a unique FPGA-Based Identification Circuit Using Process Variations Haile Yu, Philip H. W. Leong, Heiko Hinkelmann, Leandro Möller and Manfred Glesner |
|
| 11:00 | W1A3 | W1B3 | W1C3 |
| A Highly Scalable Restricted Boltzmann Machine FPGA Implementation Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMahon and Kunle Olukotun |
DPA Resistence for Light-Weight Implementations of Cryptographic Algorithms on FPGAs Rajesh Velegalati and Jens-Peter Kaps |
IP Protection in Partially Reconfigurable FPGAs Krzysztof Kepa, Fearghal Morgan and Krzysztof Kosciuszkiewicz |
|
| 11:30-12:00 | Break & Poster Session 5 | ||
|
P5.1
A Reconfigurable FIR/FFT Unit for Wireless Telecommunication Systems Maroun Ojail, Raphaël David, Stéphane Chevobbe and Didier Demigny
P5.2
Efficient AES S-boxes Implementation in Non-volatile FPGAs Lubos Gaspar, Viktor Fischer, Milos Drutarovsky, Viktor Fischer and Nathalie Bochard
P5.3
Modularizing Flux Limiter Functions for a Computational Fluid Dynamics Accelerator on FPGAs Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
P5.4
Compact FPGA Implementation of Camellia Panasayya Yalla and Jens-Peter Kaps
P5.5
FPGA-Based Acceleration of Neural Network for Ranking in Web Search Engine with a Streaming Architecture Jing Yan, Ning-Yi Xu, Xiong-Fei Cai, Rui Gao, Yu Wang, Rong Luo and Feng-Hsiung Hsu
P5.6
An FPGA Design for Evaluating Score Function in Protein Energy Calculation Jose Manuel Romero-Ximil and Arturo Díaz-Pérez
P5.7
Emulating Spiking Neural Networks for Edge Detection on FPGA Hardware Brendan Glackin, Jim Harkin, Thomas M. McGinnity, Liam P. Maguire and Qingxiang Wu
P5.8
A Reconfigurable Architecture for the Phylogenetic Likelihood Function Nikolaos Alachiotis, Alexandros Stamatakis, Euripides Sotiriades and Apostolos Dollas
P5.9
Configuring Area and Performance: Empirical Evaluation on an FPGA-based Biochemical Simulator Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichihiro Shibata, Yasunori Osana, Yuichiro Shibata, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi and Hideharu Amano
P5.10
A FPGA Based Coprocessor for Gene Finding Using Interpolated Markov Model (IMM) Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou and Apostolos Dollas
P5.11
Enhanced Gradient-Based Motion Vector Coprocessor Guillermo Botella, Antonio García, Uwe Meyer-Baese, Manuel Rodríguez, M. Carmen Molina and Luis Parrilla
P5.12
Dynamic Reconfiguration System for Real-Time Video Processing Saya Hiinaga, Yoshiki Yamaguchi, Tetsuhiko Yao and Tohru Kawabe
P5.13
Numerically Controlled Oscillators Using Linear Approximation Hans-Jörg Pfleiderer and Stefan Lachowicz
P5.14
Random Numbers Generation: Investigation of narrow transitions suppression on FPGA Vladimir Rožić and Ingrid Verbauwhede
P5.15
Improving the Quality of a Physical Unclonable Function Using Configurable Ring Oscillators Abhranil Maiti and Patrick Schaumont
P5.16
CREMA: A Coarse-grain Reconfigurable Array with Mapping Adaptiveness Fabio Garzia, Waqar Hussain and Jari Nurmi
| |||
| 12:00-13:00 | Application Acceleration #2 | Acceleration of Video Applications | |
| Session chair: Florent de Dinechin | Session chair: Jan Schier | ||
| 12:00 | W2A1 | W2B1 | W2C1 |
| FPGA Accelerating Three QR Decomposition Algorithms in the Unified Pipelined Framework Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei and Jinbo Xu |
A Toolset for the Analysis and Optimization of Motion Estimation Algorithms and Processors Trevor Spiteri, George Vafiadis and Jose Luis Nunez-Yanez |
||
| 12:30 | W2A2 | W2B2 | W2C2 |
| FPGA-Accelerated Information Retrieval: High-Efficiency Document Filtering Wim Vanderbauwhede, Leif Azzopardi and Mahmoud Moadeli |
Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3 Enrique Cantó, Mariano Fons, Mariano López and Rafael Ramos |
||
| 13:00-13:10 | Closing | ||
| 13:10-14:10 | LUNCH | ||
